A computer system may include one or more processors and memories coupled to a bus. Further, one or more input/output (I/O) devices may be coupled to the bus via an I/O interface. During operation, one or more of the processors and/or I/O devices may issue respective commands that require access to the bus. Because only one command may access the bus during a cycle, if a plurality of such commands require bus access during the same clock cycle, all or all but one of the commands may be denied bus access. Therefore, the commands must be retried (e.g., issued again at a later time). However, some or all of the commands may be retried during the same clock cycle, and therefore, all or all but one of the reissued commands must be reissued again, and so on.
To address such a problem, a conventional system may include command reissuing logic including independent sets of logic corresponding to commands from I/O devices, respectively, that may require access to the bus. When a command is retried, a set of logic corresponding to the command may create a random (e.g., pseudo-random) delay time based on a number of times the command has been retried. The command may be retried after waiting the delay time. However, such command retry logic requires a large amount of hardware, and therefore, chip real estate. Consequently, such a conventional system is costly. Accordingly, improved command retry logic and methods of using the same are desired.